Alder Lake, Golden Cove, and Gracemont Detailed

Alder Lake, Golden Cove, and Gracemont Detailed

This week Intel held its annual Structure Day occasion for choose press and companions. As with earlier iterations, the corporate disclosed particulars about its subsequent technology architectures set to return to the market over the following twelve months. Intel has promised the discharge of its next-generation client and cellular processor household, Alder Lake, to return by the tip of the 12 months and immediately the corporate is sharing variety of particulars concerning the holistic design of the chips in addition to some good element concerning the microarchitectures that type this hybrid design: Golden Cove and Gracemont. Right here is our evaluation of Intel’s disclosure.

Alder Lake: Intel 12th Gen Core

As talked about in earlier bulletins, Intel will launch its Alder Lake household of processors into each desktop and cellular platforms underneath the identify of Intel’s 12th Gen Core Processors with Hybrid Expertise later this 12 months. That is Intel’s second technology hybrid structure constructed on Intel 7 course of node know-how. The hybrid design follows Intel Lakefield designs for small notebooks launched final 12 months. The character of a hybrid design in Intel nomenclature entails having a sequence of excessive ‘Efficiency’ cores paired with quite a lot of excessive ‘Effectivity’ cores. Intel has simplified this into P-core and E-core terminology.

For Alder Lake, the processor designs characteristic Efficiency cores based mostly on a brand new Golden Cove microarchitecture, and Effectivity cores based mostly on a brand new Gracemont structure. We’ll cowl each over the course of this text, nonetheless the thought is that the P-core is preferential for single threaded duties that require low latency, and the E-core is healthier in energy restricted or multi-threaded eventualities. Every Alder Lake SoC will bodily comprise each, nonetheless Intel has not but disclosed the end-user product configurations.

Every of the P-cores has the potential to supply multithreading, whereas the E-cores are one thread per core. This implies there shall be three bodily designs based mostly on Alder Lake:

  • 8 P-core + 8 E-core (8C8c/24T) for desktop on a brand new LGA1700 socket
  • 6 P-core + 8 E-core (6C8c/20T) for cellular UP3 designs
  • 2 P-core + 8 E-core (2C8c/12T) for cellular UP4 designs

Intel sometimes highlights UP4 cellular designs for very low energy installs, right down to 9 W, whereas UP3 can cowl something from 12 W to 35 W (or maybe larger), however when requested concerning the energy budgets for these processors, Intel acknowledged that extra element will comply with when product bulletins are made. Intel did affirm that the best shopper energy, presumably on the desktop processor, shall be 125 W.

Highlighted in our discussions is how modular Intel has made Alder Lake. From a variety of base element choices, the corporate blended and matched what it felt have been the perfect mixture of components for every market.

Right here it reveals that 4 E-cores takes up the identical bodily house as one P-core, but additionally that the desktop {hardware} will at most have 32 EUs (Execution Items) for Xe-LP graphics (identical because the earlier technology), whereas each of the cellular processors will provide 96 bodily EUs that could be disabled down based mostly on the precise line merchandise within the product stack.

All three processors will characteristic Intel’s subsequent technology Gaussian Neural Accelerator (GNA 3.0) for minor low energy AI duties, a show engine, and a few degree of PCIe, nonetheless the desktop processor could have extra. Solely the cellular processors will get an Picture Processing Unit (IPU), and Thunderbolt 4 (TBT), and right here the large UP3 cellular processor will get 4 ports of Thunderbolt whereas the smaller UP4 will solely get two. The desktop processor is not going to have any native Thunderbolt connectivity.

A bit extra information on the Desktop Processor IO and Interconnect

We’ll cowl a bit extra element concerning the core designs later on this article, however Intel did showcase among the data on the desktop processor. It confirmed explicitly that there could be 16 complete cores and 24 threads, with as much as 30 MB of non-inclusive final degree/L3 cache.

In distinction to earlier iterations of Intel’s processors, the desktop processor will assist all trendy requirements: DDR5 at 4800 MT/s, DDR4-3200, LPDDR5-5200, and LPDDR4X-4266. Alongside this the processor will allow dynamic voltage-frequency scaling (aka turbo) and provide enhanced overclocking assist. What precisely that final aspect means we’re unclear of at this level.

Intel confirmed that there’ll not be separate core designs with totally different reminiscence assist – all desktop processors could have a reminiscence controller that may do all 4 requirements. What this implies is that we might even see motherboards with built-in LPDDR5 or LPDDR4X somewhat than reminiscence slots if a vendor needs to make use of LP reminiscence, principally seemingly in built-in small type issue designs however I wouldn’t put it previous somebody like ASRock to supply a mini-ITX board with inbuilt LPDDR5. It was not disclosed what reminiscence architectures the cellular processors will assist, though we do count on nearly an identical assist.

On the PCIe aspect of issues, Alder Lake’s desktop processor shall be supporting 20 lanes of PCIe, and that is break up between PCIe 4.0 and PCIe 5.0.

The desktop processor could have sixteen lanes of PCIe 5.0, which we count on to be break up as x16 for graphics or as x8 for graphics and x4/x4 for storage. This can allow a full 64 GB/s bandwidth. Above and past this are one other 4 PCIe 4.0 lanes for extra storage. As PCIe 5.0 NVMe drives come to market, customers might need to resolve if they need the total PCIe 5.0 to the discrete graphics card or not

Intel additionally let it’s identified that the highest chipset for Alder Lake on desktop now helps 12 lanes of PCIe 4.0 and 16 lanes of PCIe 3.0. This can enable for extra PCIe 4.0 units to make use of the chipset, lowering the variety of lanes wanted for gadgets like 10 gigabit Ethernet controllers or something a bit spicier. For those who ever thought your RGB controller might use extra bandwidth, Intel is just blissful to supply.

Intel didn’t disclose the bandwidth connectivity between the CPU and the chipset, although we imagine this to be not less than PCIe 4.0 x4 equal, if not larger.

The Alder Lake processor retains the dual-bandwidth ring we noticed carried out in Tiger Lake, enabling 1000 GB/s of bandwidth. We discovered from asking Intel in our Q&A that this ring is absolutely enabled no matter whether or not the P-cores or E-cores are getting used – Intel can disable one of many two rings when much less bandwidth is required, which might save energy, nonetheless based mostly on earlier testing this single ring might find yourself drawing substantial energy in comparison with the E-cores in low energy operation. (This can be true within the cellular processors as nicely, which might have knock on results for cellular battery life.)

The 64 GB/s of IO cloth is according to the PCIe 5.0 x16 numbers we noticed above, nonetheless the 204 GB/s of reminiscence cloth bandwidth is a complicated quantity. Alder Lake encompasses a 128-bit reminiscence bus, which permits for 4x 32-bit DDR5 channels (DDR5 has two 32-bit channels per module, so 2 modules nonetheless), nonetheless with the intention to attain 204 GB/s in that configuration requires DDR5-12750; Intel has rated the processor solely at DDR5-4800, lower than half that, so it’s unclear the place this 204 GB/s quantity comes from. For perspective, Intel’s Ice Lake does 204.8 GB/s, and that’s a high-power server platform with 8 channels of DDR4-3200.

This closing slide mentions TB4 and Wi-Fi 6E, nonetheless as with earlier desktop processors, these are derived from controllers connected to the chipset, and never within the silicon itself. The cellular processors could have TBT built-in, however the desktop processor doesn’t.

This slide additionally mentions Intel Thread Director, which we wish to tackle on the following web page earlier than we get to the microarchitecture evaluation.

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