with 4nm, 3nm, 20A and 18A?!

with 4nm, 3nm, 20A and 18A?!

In in the present day’s Intel Accelerated occasion, the corporate is driving a stake into the bottom concerning the place it needs to be by 2025. CEO Pat Gelsinger earlier this 12 months acknowledged that Intel can be returning to product management in 2025, however hasn’t but defined how that is coming about – that’s till in the present day, the place Intel has disclosed its roadmap for its subsequent 5 generations of course of node know-how resulting in 2025. Intel believes it may possibly observe an aggressive technique to match and go its foundry rivals, whereas on the similar time growing new packaging choices and beginning a foundry enterprise for exterior prospects. On high of all this, Intel has renamed its course of nodes.

The Quick Reply:

In case you solely take one factor away from this text, I will put it right here entrance and middle. Here’s what we’re seeing for Intel’s roadmaps, primarily based on their disclosures in the present day.

As at all times, there’s a distinction between when a know-how ramps for manufacturing and involves retail; Intel spoke about some applied sciences as ‘being prepared’, whereas others had been ‘ramping’, so this timeline is solely these dates as talked about. As you may think, every course of node is prone to exist for a number of years, this graph is solely showcasing the main know-how from Intel at any given time.

In order for you the small print on this graph, then learn on.

Intel’s Defines a Robust Future: Is TSMC at Danger?

Earlier this 12 months, CEO Pat Gelsinger introduced Intel’s new IDM 2.0 technique, consisting of three parts:

  1. Construct (7nm)
  2. Develop (TSMC)
  3. Productize (Intel Foundry Companies)

The aim right here is to proceed to work on Intel’s course of node know-how improvement, going past the present 10nm designs in manufacturing in the present day, however concurrently utilizing different foundry companies from companions (or rivals) to regain/retain Intel’s place in its processors that drive a number of the corporate income. The third ingredient is IFS, Intel’s Foundry Companies, the place Intel is committing in an enormous approach to opening up its manufacturing services to exterior semiconductor enterprise.

Underpinning (1) and (3) is how Intel executes by itself course of node improvement. Whereas in Intel’s current Q3 2021 earnings name CEO Gelsinger confirmed that Intel is now producing extra 10nm wafers in a day than 14nm wafers, marking a shift in confidence between the 2 designs, it’s no secret that Intel has had problem in transitioning from its 14nm course of to its 10nm course of. On June 29th this 12 months, Intel additionally acknowledged that its subsequent technology 10nm product requires extra validation time to streamline deployment on enterprise methods for 2022. Be aware that on the similar time, TSMC has surpassed Intel by transport at capability with its equal designs (known as 7nm) and its vanguard (5nm) designs that surpass Intel’s efficiency.

As with the earlier announcement in March, Intel is reaffirming that it intends to return to management efficiency in semiconductors in 2025. This may allow each the corporate to compete higher because it builds its personal merchandise (1) but in addition provide a wider portfolio of efficiency and applied sciences for its future IFS prospects (3). To do that, it’s realigning the roadmap for its future course of node applied sciences to be extra aggressive with enhancements, but on the similar time extra modular with its know-how to allow quicker transitions.

Main up this plan is Dr. Ann B Kelleher, who was named SVP and GM of the Know-how Improvement division at Intel final 12 months. This division is the place all of the analysis and improvement of Intel’s future course of node applied sciences and enhancements comes from – it was a part of Intel’s System Structure Group, nevertheless it was break up in July 2020 to re-establish a spotlight purely on Know-how Improvement. Dr. Kelleher’s background includes course of analysis in academia, adopted by 26 years at Intel as a course of engineer, transferring as much as managing Fab 24 in Eire, Fab 12 in Arizona, Fab 11X in Rio Rancho, earlier than touchdown in HQ in Oregon because the GM of Manufacturing and Operations.

Her expertise overlaying each fab-scale manufacturing and course of node analysis goes to be essential for Intel’s future plans. In discussing with Kelleher forward of in the present day’s bulletins, she acknowledged that she has applied elementary adjustments in the case of provider method, ecosystem learnings, organizational adjustments, modular design methods, contingency plans, and realigning the Know-how Improvement Group right into a extra streamlined outfit able to execute. These embrace key personnel corresponding to Sanjay Natarajan as SVP and GM of Logic Improvement (one in all Intel’s current rehires) and Babak Sabi as CVP and GM of Meeting/Take a look at Improvement

Intel is in the present day defining ‘know-how management by 2025’ as outlined by the metric of efficiency per watt. We requested Intel is a pre-briefing what which means for peak efficiency, which is commonly a metric we care about for finish product design, and the reply was that “peak efficiency stays a key a part of Intel’s strategic improvement”.

Intel Renames The Nodes: ‘Mine is Smaller’

The issue with merely posting Intel’s roadmap right here is that the information is two-fold. Not solely is Intel disclosing the state of its know-how for the following a number of years, however the names of the know-how are altering to higher align with widespread trade norms.

It’s no secret that having “Intel 10nm” being equal to “TSMC 7nm”, although the numbers truly don’t have anything to do with the bodily implementation, has floor at Intel for some time. Numerous the trade, for no matter cause, hasn’t discovered that these numbers aren’t truly a bodily measurement. They was, however once we moved from 2D planar transistors to 3D FinFET transistors, the numbers grew to become nothing greater than a advertising and marketing instrument. Regardless of this, each time there’s an article in regards to the know-how, folks get confused. We’ve been speaking about it for half a decade, however the confusion nonetheless stays.

To that finish, Intel is renaming its future course of nodes. Right here’s the roadmap picture, however I’ll be breaking it down piece by piece.

2020, Intel 10nm SuperFin (10SF): Present technology know-how in use with Tiger Lake and Intel’s Xe-LP discrete graphics options (SG1, DG1). The identify stays the identical.

2021 H2, Intel 7: Beforehand often known as 10nm Enhanced Tremendous Fin or 10ESF.  Alder Lake and Sapphire Rapids will now be often known as Intel 7nm merchandise, showcasing a 10-15% efficiency per watt acquire over 10SF resulting from transistor optimizations. Alder Lake is at present in quantity manufacturing. Intel’s Xe-HP will now be often known as an Intel 7 product.

2022 H2, Intel 4: Beforehand often known as Intel 7nm. Intel earlier this 12 months acknowledged that its Meteor Lake processor will use a compute tile primarily based on this course of node know-how, and the silicon is now again within the lab being examined. Intel expects a 20% efficiency per watt acquire over the earlier technology, and the know-how makes use of extra EUV, principally within the BEOL. Intel’s subsequent Xeon Scalable product, Granite Rapids, may also use a compute tile primarily based on Intel 4.

2023 H2, Intel 3: Beforehand often known as Intel 7+. Elevated use of EUV and new excessive density libraries. That is the place Intel’s technique turns into extra modular – Intel 3 will share some options of Intel 4, however sufficient will likely be new sufficient to explain this a brand new full node, specifically new excessive efficiency libraries. Nonetheless, a quick observe on is anticipated. One other step up in EUV use, Intel expects a producing ramp within the second half of 2023 with an 18% efficiency per watt acquire over Intel 4.

2024, Intel 20A: Beforehand often known as Intel 5nm. Transferring to double digit naming, with the A standing for Ångström, or 10A is the same as 1nm. Few particulars, however that is the place Intel will transfer from FinFETs to its model of Gate-All-Round (GAA) transistors known as RibbonFETs. Additionally Intel will debut a brand new PowerVia know-how, described beneath.

2025, Intel 18A: Not listed on the diagram above, however Intel is anticipating to have an 18A course of in 2025. 18A will likely be utilizing ASML’s newest EUV machines, often known as Excessive-NA machines, that are able to extra correct photolithography. Intel has acknowledged to us that it’s ASML’s lead accomplice in the case of Excessive-NA, and is ready to obtain the primary manufacturing mannequin of a Excessive-NA machine. ASML just lately introduced Excessive-NA was being delayed- when requested if this was a difficulty, Intel mentioned no, because the timelines for Excessive-NA and 18A are the place Intel expects to intersect and have unquestioned management.

Intel has confirmed to us that Intel 3 and Intel 20A will likely be provided to foundry prospects (however hasn’t acknowledged if Intel 4 or Intel 7 will likely be).

To convey this altogether in a single desk, with identified merchandise, now we have the next:

Intel’s Course of Node Know-how
Previous Identify New Identify Roadmap Merchandise Options
10SF 10SF At present Tiger Lake
SG1
DG1
Xe-HPC Base Tile
Agilex-F/I FPGA
SuperMIM
Skinny Movie Barrier
Quantity 10nm
On sale in the present day
10ESF Intel 7 2021 H2 merchandise Alder Lake (21)
Raptor Lake (22)?
Sapphire Rapids (22)
Xe-HP
Xe-HPC IO Tile
10-15% PPW
Upgraded FinFET
ADL in Ramp in the present day
7nm Intel 4 2022 H2 ramp
2023 H1 merchandise
Meteor Compute Tile
Granite Compute Tile
20% PPW vs 7
Extra EUV
Silicon in Lab
7+ Intel 3 2023 H2 merchandise 18% PPW vs 4
Space Financial savings
Extra EUV
New Perf Libraries
Sooner Comply with On
5nm Intel 20A 2024 RibbonFET
PowerVia
5+ Intel 18A 2025 Unquestioned Management 2nd Gen Ribbon
Excessive NA EUV

One of many points right here is the distinction between a course of node being prepared, ramping manufacturing for product launches, and truly being made obtainable. For instance, Alder Lake (now on Intel 7nm) is because of come out this 12 months, however Sapphire Rapids goes to be extra of a 2022 product. Equally, there are studies of Raptor Lake on Intel 7 popping out in 2022 to exchange Alder Lake with the tiled Meteor Lake on Intel 4 in 2023. Whereas Intel is blissful to debate course of node improvement time frames, product timeframes will not be as open (as little doubt prospects would get pissed off if the time acknowledged is missed).

Why The Nodes Have been Renamed

In order acknowledged earlier than, one ingredient of renaming the nodes is because of matching parity with different foundry choices. Each TSMC and Samsung, rivals to Intel, had been utilizing smaller numbers to check comparable density processes. With Intel now renaming itself, it will get extra in-line with the trade. That being mentioned, maybe sneakily, Intel’s 4nm is perhaps on par with TSMC’s 5nm, reversing the tables. By 3nm we anticipate there to be a superb parity level, nevertheless that can depend upon Intel matching TSMC’s launch schedule.

Quite than throw course of node names all over the place, it’s typical to check with peak quoted transistor densities as a substitute. Right here is the desk we revealed in our current IBM 2nm information submit, however with an up to date shift on Intel’s naming.

2021 Peak Quoted Transistor Densities (MTr/mm2)
AnandTech
Course of Identify
IBM TSMC Intel Samsung
22nm     16.50  
16nm/14nm   28.88 44.67 33.32
10nm   52.51 100.76 51.82
7nm   91.20 100.76 95.08
5/4nm   171.30 ~200* 126.89
3nm   292.21*    
2nm / 20A 333.33      
Knowledge from Wikichip, Completely different Fabs might have completely different counting methodologies
* Estimated Logic Density

Precisely the place Intel’s new 4nm and beneath will find yourself is but to be disclosed, as numbers with stars alongside are primarily based on estimates by the respective corporations.

It has been anticipated for some time that Intel can be realigning its course of node naming. Behind closed doorways, I personally have been lobbying for it for some time, and I do know that a couple of different journalists and analysts have been suggesting it to Intel as nicely. Some responses we acquired had been associated to apathy – one government advised me that “our prospects that care about this truly know the distinction”, which is true for positive, however what we’re speaking about right here is extra about notion within the wider ecosystem for fans and monetary analysts who won’t be in control. It is kind of a branding train, and I additionally advised Intel that they’re going to should anticipate a blended response – some voices would possibly interpret the transfer as Intel attempting to drag one over in the marketplace, for instance. However they’re going to should stay with it, as these are the brand new names.

In the meantime, regardless of Intel’s struggles with 10nm, it’s nonetheless a course of node in manufacturing and in quantity manufacturing, in use for each client and enterprise units, and it is coming to desktops very quickly. Regardless that it has some stiff competitors from different gamers, it’s nonetheless an providing available in the market, and for those who wish to examine course of node densities utilizing these names, it ought to have a moniker to keep away from confusion. I’m applauding that Intel is doing it sooner relatively than later.

One key level to notice is that the brand new Intel 7 node, which was previously the 10ESF node, shouldn’t be essentially a “full” node replace as we sometimes perceive it. This node is derived as an replace from 10SF, and because the diagram above states, could have ‘transistor optimizations’. Transferring from 10nm to 10SF, that meant SuperMIM and new skinny movie designs giving an additional 1 GHz+, nevertheless the precise particulars from 10SF to the brand new Intel 7 is unclear at this level. Intel has nevertheless acknowledged that transferring from Intel 7 to Intel 4 will likely be an everyday full node bounce, with Intel 3 utilizing modular components of Intel 4 with new excessive efficiency libraries and silicon enhancements for one more bounce in efficiency.

We requested Intel if these course of nodes could have extra optimization factors, and had been advised that they’ll – whether or not any of them will likely be explicitly productized will depend upon the options. Particular person optimizations might account for an extra 5-10% efficiency per watt, and we had been advised that even 10SF (which retains its identify) has had a number of extra optimization factors that haven’t essentially been publicized. So whether or not these updates get marketed as 7+ or 7SF or 4HP shouldn’t be identified, however as with all manufacturing course of as updates happen to assist enhance efficiency/energy/yield, they get utilized assuming the design adheres to the identical guidelines.

“Is not Intel Simply Making an attempt To Pull The Wool Over Our Eyes?”

No.

The issue right here is that there isn’t a constant node naming between foundries. Intel has been saving any quantity change for main advances in its node manufacturing know-how, as a substitute utilizing +/++ to suggest enhancements. If we examine this to TSMC and Samsung, each of whom have been blissful to offer half-node jumps new numbers fully.

For instance, Samsung’s 7LPP is a significant node, nevertheless 6LPP, 5LPE and 4LPE are all iterative efforts on the identical design (arguably additionally iterative of 8LPP), with 3GAE being the following main bounce. Examine this to Intel, who was planning 10nm to 7nm to 5nm as main course of node jumps – so whereas Samsung had one bounce deliberate and 4 sub-variants (or extra), Intel had two main jumps. Equally, TSMC’s 10nm was a half-node bounce over 16nm, whereas 16nm to 7nm was the total node – Intel made 14 to 10 to 7 as full nodes.

Intel caught to its weapons a protracted whereas, and delays to 10nm successfully harm it in a multiplicative style. For instance, if Intel had labeled 14+ as 13nm, and 14++ as 12nm, maybe it would not be so unhealthy. I imply, sure Intel ought to anticipate some harm for 10nm being late, however when different foundries had been showcasing smaller steps as full quantity jumps, it grew to become a advertising and marketing and media nightmare. 14++++ grew to become an trade joke, and paired with how each time after they talked about future course of nodes they needed to cite the equal TSMC of Samsung course of, it obtained a bit an excessive amount of. It needed to be defined each time, as new folks come into the trade.  

I’ve lobbied Intel to regulate its naming for some time, and I do know different friends have as nicely. After we check with Intel 7 any further, we will draw equivalents to TSMC 7nm (even when TSMC is transport 5nm in quantity) with out having to extensively clarify variations in a easy identify. This is not Intel pulling the wool over your eyes, or attempting to cover a nasty scenario. That is Intel catching as much as the remainder of the trade in how these processes are named. So as to add to this, it is a good factor that Intel is barely renaming future nodes that have not reached the market but.

This can be a multi-page article!

Click on the dropdown beneath for extra pages, together with

  1. This Web page, New Node Names
  2. A Sidebar on Intel EUV and changing into ASML Lead Companion
  3. New for 2024: RibbonFETs and PowerVias
  4. Subsequent Gen EMIB and Foveros Packaging
  5. Clients Clients Clients

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