Dr. Kevin Zhang and Dr. Maria Marced

Dr. Kevin Zhang and Dr. Maria Marced

Prior to now week, TSMC ran its 2021 Know-how Symposium, masking its newest developments in course of node expertise designed to enhance the efficiency, prices, and capabilities for its clients. On this occasion, TSMC mentioned its growing use of Excessive Extremely Violet (EUV) lithography for manufacturing, enabling it to scale all the way down to its 3nm course of node, effectively past that of its opponents. TSMC additionally addressed the present points surrounding demand for semiconductors, together with asserting that it’s constructing new services for superior packaging manufacturing. Becoming a member of CEO Dr. CC Wei as a part of the keynote presentation was AMD’s CEO Dr. Lisa Su, Qualcomm’s President (and shortly to be CEO) Cristiano Amon, and Ambiq’s Founder and CTO Scott Hanson.

As a part of the proceedings, TSMC provided AnandTech a 30-minute interview with Dr. Kevin Zhang, SVP of Enterprise Growth, and Dr. Maria Marced, President of TSMC EU, as a chance to study extra about TSMC’s driving instructions in addition to cooperation with trade companions. TSMC did request that we preserve the questioning solely on expertise issues and associated to the bulletins at its Know-how Symposium, somewhat than focus on present world political matters.

Kevin Zhang

SVP Enterprise Growth

Maria Marced

President, TSMC EU

Ian Cutress


Dr. Kevin Zhang has been TSMC’s Senior Vice President of Enterprise Growth for nearly a 12 months, having being promoted from the Design Know-how Crew. Earlier to becoming a member of TSMC, Dr. Zhang spent 11 years at Intel as an Intel Fellow, changing into Vice President of the Know-how and Manufacturing Group in addition to Director of Circuit Know-how. Dr. Zhang has printed over 80 papers in technical conferences and analysis journals, holds 55 patents in built-in circuit expertise, and holds a PhD in Electrical Engineering. Dr. Zhang would be the convention chair for ISSCC 2022.

Dr. Maria Marced is President of TSMC Europe, answerable for driving technique and growth of the corporate within the area, and has been within the place since 2007. Previous to this, Dr. Marced spent 4 years at NXP and 19 years at Intel in related top-position roles. Dr. Marced serves because the Chairwoman of the EMEA Management Council of the GSA (International Semiconductor Alliance), is on the board of CEVA, and holds a PhD in Telecommunications Engineering.


TSMC on The Main Edge

Ian Cutress: TSMC has said that it has had in-house EUV pellicle manufacturing since 2019, and TSMC is now vastly ramping up manufacturing of pellicles. How intensive is the use in manufacturing, and the way does it additional TSMC’s aggressive benefit versus different fabs?

Kevin Zhang: We clearly have invested on this space in-house, and I feel it’s a very distinctive expertise for us. We’re capable of leverage it to convey up our EUV mass manufacturing. For those who take a look at the best way we ran our 7 nm, on the 6 nm, and now in 5 nm, all with the EUV, clearly we have now made large progress. So that is undoubtedly an space we expect we have now executed effectively with our distinctive expertise benefit.

Maria Marced: One factor, as a result of I’m right here in Amsterdam, so we’re comparatively near ASML – we have now had particular coaching by them. I can let you know, having this manufacturing in-house actually permits us to increase the lifetime of the masks. Sometimes in EUV, the masks will get soiled, and subsequently, with brief deadlines, this actually helps us loads to enhance the productiveness of EUV and the masks.

IC: So by having it on website means you’ve bought much less journey for the masks, and it will get much less soiled because of much less journey?

MM: That’s appropriate.


IC: We sometimes affiliate complicated and specialty applied sciences with forefront clients. On condition that these clients are sometimes within the low single digits, how does TSMC steadiness what packaging applied sciences to develop that clients want, in comparison with growing and pathfinding new applied sciences?

KZ: On the main node, for instance, we have now been a pacesetter – a expertise chief. We need to proceed to drive development of silicon expertise, and we companion with our lead clients to optimize our expertise. So that is undoubtedly an space we proceed to drive the long run development. However with that being mentioned, I nonetheless suppose specialty expertise additionally performs an important function in our general expertise providing to our clients.  A lot of our clients can’t ship a single chip based mostly on as an instance, 5 nm, with out possibly a 20 nm companion chip. For those who take a look at a cellphone for instance, there are a number of chips, and lots of companion chips. It’s the similar factor with automotive – you will have a complicated chip there, however you additionally want lots of microcontrollers based mostly on mature expertise. 

So I feel we have now been doing a superb job in balancing our general expertise growth effort. Now we have invested in mature expertise considerably over the previous many years. For those who take a look at our general expertise roadmap, we’re offering essentially the most superior specialty expertise providing right this moment within the market. I feel Maria possibly will add some colour from a Europe perspective.

MM: The one factor I’ll add is that it is vitally essential for us to know the system complexity of our clients. Additionally, particularly by having these applied sciences that full the invoice of supplies of the entire system, it helps us to raised perceive how the system architectures are evolving, and subsequently do a greater job for our clients.

IC: So how a lot of that goes all the way down to what clients are particularly demanding, versus researching new applied sciences that clients do not know they want but?

KZ: Now we have a separate staff, for instance, from a company perspective. Now we have a separate staff, a analysis staff taking a look at issues past the following technology. We actually look far out for that to discover various things. It additionally requires numerous market enter, and buyer enter. to assist information among the exploratory work. So it is a fairly dynamic course of, very interactive between us, inside us, and between us and the purchasers.


IC: TSMC has been very clear in saying that it’s staying with FinFET, down to three nm, and transferring to Gate-All-Round at 2 nm. In contrast, the competitors is transferring to GAA at an earlier stage of growth. Are you able to describe how TSMC is weighing each its need to be on the vanguard of those superior applied sciences, but additionally sustaining the identical FinFET for its manufacturing strains?

KZ: The explanation we selected FinFET expertise as a 3 nm relies on two issues. 

One, we have now to determine a approach to enhance the expertise into extra energy effectivity, extra efficiency, and the interior density. Ultimately the client does not care whether or not it’s FinFET, or Nanosheet. They need to take a look at it from their product perspective – about what sort of energy, efficiency, and density profit it may possibly convey to the client. That is a very powerful factor ultimately.  So we take a look at our FinFET expertise, and we take a look at our innovation functionality, we discover a very very highly effective knob, an revolutionary knob, that enables us to increase the FinFET expertise down to three nm whereas additionally attaining substantial full node scaling advantages. In order that’s cause primary. 

Cause quantity two can be the schedule. We need to be sure, on the proper given time, we’re capable of ship essentially the most superior expertise. So predictability, from a complicated expertise growth perspective, may be very crucial. Our clients take scheduling very severely! So combining the 2, we decided to stick with the FinFET at 3nm. We imagine within the 2022-2023 timeframe, our 3 nm will convey essentially the most superior logic expertise to {the marketplace}.



IC: How do you steadiness pushing course of density versus design complexity, similar to 1D versus 2D steel routing? What are the present potentialities on main nodes?

KZ: We take a look at all of the completely different metrics. On the finish of the day, we think about actually what it’s at a product stage, at a system stage, and how much general scaling profit we will convey the client. Once I speak concerning the scaling advantages, I discuss with general energy/efficiency and the prices. This must be executed on the system stage, it is not merely on the chip stage. 

Prior to now, two dimensional scaling dominated all the things, however now we have now to look extra at a system stage. For instance, you discover that we spend lots of effort and funding growing chip stage integration schemes: we have now 2D, 2.5D, and 3D going ahead. This all comes into play to mainly present an entire system stage answer for the long run. I feel you will note increasingly more purposes based mostly on refined superior chip stage integration expertise. Transistor growth continues to be essential, make no mistake, and it will proceed to be very crucial. Offering the client the most effective vitality environment friendly transistors remains to be very crucial, however that is not going to be ample. 

We take a look at general scaling on the system stage. So numerous co-optimization between expertise, completely different elements of the expertise, and the product system stage design.


IC: As course of nodes shrink, resistance on steel layers is changing into extra problematic. With regards revolutionary options, and unique supplies versus copper interconnects, is it only a case of extra analysis down that entrance? Or do we have to put extra effort into growing and routing increased steel layers?

KZ: I feel within the analysis session at our superior expertise introduction, we did cowl a bit bit concerning the again finish work. For instance, we’re persevering with to optimize the copper grain boundary to convey a decrease resistance steel line to our general chip expertise and new expertise. Additionally, with dielectrics we proceed to seek out revolutionary supplies to enhance the dielectric in parasitic capacitance. So, these issues are being actively researched. 

The 3D integration may also convey another answer to this complete efficiency requirement within the back-end. You’ll be able to as an alternative route from A to B in a 2 dimensional area, or you possibly can route A to B vertically in 3 dimensions. In some instances, by going vertical, you possibly can scale back the general size of the RC wire, and scale back move delay considerably. So all these issues must be checked out going ahead.

IC: So trying into new applied sciences, the 2 most promising applied sciences as we transcend Gate-All-Round are 2D transistors and carbon nanotubes. TSMC just lately launched a paper that bought lots of press relating to new developments on 2D transistors. Are you able to touch upon what seems to be extra promising?

KZ: All these superior supplies for transistors have sure benefits. That is why we spend early R&D efforts to discover these, however these are nonetheless fairly far out. There are lots of issues that also have to be higher understood, particularly as it’s going to take large effort to convey these sorts of latest supplies, and new constructions, right into a large-scale manufacturing base. So there may be nonetheless lots of work forward of us. However the good factor is we’re not missing in  new concepts. There are many new issues we’re exploring, and so they all have a sure benefit. So we simply want to determine find out how to combine all of them collectively to convey out essentially the most compelling general expertise answer to our future clients’ purposes.

IC: Concerning the analysis in collaboration with ASML, they’ve spoken about future EUV developments similar to excessive NA (numerical aperture) optics. They preserve speaking to us about it! However as an extension of that, are you able to talk about what TSMC is essentially doing relating to post-EUV applied sciences?

KZ: We take a look at all completely different expertise choices. We talked a bit bit on the convention about materials improvements to convey new supplies built-in on the silicon to permit us to attain higher conduction and a extra energy environment friendly transistor. These are essential areas by which we have now a analysis staff and an early R&D staff to develop and discover all completely different choices. 

On lithography, clearly it continues to be an important half in scaling the geometry. So we do have a staff additionally trying into find out how to maximize EUV, to print even tighter pitches going ahead. All these issues are being explored for the way forward for expertise choices.



Going Past Asia

IC: With reference to these most superior applied sciences, and forefront capabilities, for Europe we have heard that the opponents of TSMC are investing of their European services. We have not essentially heard the identical from TSMC. Is there a specific cause for this? Or is there one thing that’s to be introduced? 

MM: Properly, we wouldn’t rule out something. Nevertheless, right this moment, I do not need any particulars to share with you!


IC: In your European clients – only some of them are sort of on the vanguard? Most of them depend on the older course of applied sciences, specialty applied sciences – similar to the massive automotive trade in Germany. We do not essentially see that there is lots of need to go forefront from European enterprise. Are you able to remark?

MM: The primary segments in Europe are automotive, industrial, but additionally the place Europe is essential as effectively is within the Web of Issues (IoT). The applied sciences which are required by these segments are extra on the specialty aspect, and extra on the superior, not solely mature, however superior applied sciences.

IC: We’re clearly seeing lots of semiconductor demand for AI. A number of clients need forefront options, however there may be additionally numerous demand for edge merchandise on the extra mature nodes. Are you able to speak to developments on how demand is shifting relating to AI, and maybe a point out of the EU provided that China and North America will get the highlight? 

MM: Properly, even within the UK, you will have good AI corporations! You recognize that one in every of them is one in every of our early adopter clients in a number of initiatives (Ian: Graphcore already introduced working with TSMC at 3nm). But in addition in Israel, we see lots of exercise round AI. So in EMEA we see lots of curiosity in synthetic intelligence, and even the EU has some exercise leaning in direction of what they name the European Processor Initiative (EPI), which revolves round the usage of synthetic intelligence. 

So sure, we see lots of exercise. Really, right this moment, I used to be very proud that in my presentation on the convention, I bought an electronic mail from Matteo Vallejo from the College in Barcelona, which may be very a lot concerned in AI. So after all, China and the US are all the time very superior in excessive efficiency computing, however we additionally see lots of curiosity in Europe, and lots of VC cash in AI.

IC: TSMC likes to advertise the place the income is coming from, and the proportion of income it receives from North America appears to be growing, on the expense of the proportion from Europe. Are there any headwinds or tailwinds about Europe that we should always take into consideration? 

MM: The primary cause I feel is that as a result of Europe’s principal segments are automotive, industrial, and IoT. These segments are nonetheless utilizing mature superior applied sciences, and specialty applied sciences, and lots of these end-products have a decrease ASP, and this creates an enormous distinction when it comes to the proportion of revenues. How is that this transferring ahead? Quick, as a result of automotive, in addition to industrial, particularly as a part of trade 4.0 and IoT, are as a result of AI choices are transferring quick in direction of extra superior, extra forefront expertise. So I actually anticipate that this proportion goes to alter considerably sooner or later.


IC: TSMC has three principal geographical areas – TSMC Asia, TSMC North America, and TSMC EMEA. How a lot are these unbiased group from one another – how a lot collaboration happens? Is it proper to be cut up, provided that corporations typically work worldwide or in a number of markets?

MM: Oh that is an fascinating query! I actually imagine in corporations being centralized, having labored at Intel for a few years (Maria was at Intel for 19 years), I actually imagine in corporations being centralized and having one path coming from the management of the corporate. So we’re not unbiased organizations in any respect! We’re very depending on one another, and I can let you know I often spend most of my time touring to Taiwan – now video conferencing with Taiwan. However completely we have now one path, and we complement one another very effectively. I feel Europe is bringing one thing completely different, which is concentrated extra on and round specialties. That is the place we play the important thing function. We’re actually one firm with one path.




Constructing and Increasing

IC: Pivoting to packaging, the CEO talked about that there are 5 fabs enabling SoIC and a brand new fab in Chunan with extra capability. Usually we measure manufacturing fabs in wafers per 30 days, so how ought to we think about the throughput of those new SoIC services?

KZ: I am unable to provide you with a particular capability quantity, however all that I can say is that we’re actually investing in our backend functionality and capacities. It’s because we do see a development that increasingly more clients need to leverage our superior packaging choices, together with CoWoS, InFO, and going ahead, SoIC with 3D integration. In order that’s why we’re investing not solely within the R&D aspect, however we’re additionally investing within the capability aspect to organize for future development.

With 3D packaging capability metrics, it will depend on what sort of configuration you do. Generally you would probably do a really superior chiplet built-in with extra mature nodes, and minus one or minus two nodes, so that you just most likely must compute the whole quantity otherwise. All of it will depend on the precise product configuration. Possibly sooner or later, we’ll have to determine a technique to higher measure the quantity and report the numbers. For the definition quantity, once you come to 3D integration, it could be that we rely the variety of last built-in components.

IC: TSMC presently has 4 packaging services, and this fifth one (referred to as AP6) is being in-built Chunan. AP6 would have over 50% of the packaging capability of TSMC globally. Are there any optimistic or unfavorable implications for having a big portion of all TSMC’s packaging in a single space? 

KZ: We do lots of balancing – there’s a bonus for us by constructing a bigger scale manufacturing facility. I feel you most likely already know that we construct Gigafabs right this moment with massive scales. I feel that that is a key financial profit that we will convey to our clients, enabling decrease prices that may even be handed on to the client. However we do must have concerns on find out how to unfold that to completely different places. We’re doing that, ensuring we keep a sure steadiness. In the same gentle, we’re constructing a manufacturing unit in Arizona fairly distant from Taiwan! 

IC: Talking about packaging and OSAT bottlenecks. When talking with our viewers, various them appear to suppose it’s wafer throughput, and a few of them imagine it comes all the way down to packaging throughput. I do not essentially need to ask you about which one is essentially the most bottlenecked however I do need to ask about how TSMC is enhancing throughput of buyer orders. We’ve spoken about TSMC increasing its packaging, however is there something TSMC can do right here?

KZ: I feel on the technical half, your readers need to view it as both the wafer expertise is the bottleneck, or the packaging applied sciences are the bottleneck. Really the best way I take a look at it’s how we’re discovering the optimum answer to convey all of the items collectively at a system stage to offer the most effective consequence. For those who look again at semiconductor expertise, it began with two dimensional issues, and Moore’s legislation is concerning the transistor density, scaling, and economics. However now as we’re transferring ahead, I see the entire trade trending as we transfer in direction of a better stage of integration. In technical conferences, similar to ISSCC, you see individuals not solely speak about transistor stage design, however additionally they speak about system stage efficiency, and find out how to convey the entire features and all of the items collectively. Sooner or later, I feel that this development will proceed, so it is actually about working together with your clients for his or her given product software, given their distinctive system stage necessities, and the way you convey the entire items collectively in an optimum style. That is how I take a look at it sooner or later.

MM: Our key factor is that we collaborate to innovate. Collaborating with our clients is our greatest technique to actually innovate, permitting their improvements and on the similar time boosting our personal improvements.

IC: DTCO (Design Know-how Co-Optimization) is an integral a part of making most out of forefront applied sciences. Is DTCO getting extra complicated, or as TSMC and its clients perceive the method behind attaining good DTCO, is it accelerating? Are you able to speak about that?

KZ: I feel our clients have benefited vastly from design expertise co-optimization during the last couple of generations. Going ahead, there might be extra DTCO to do, and we discover our clients are extra keen and prepared to collaborate with us as a way to harvest intrinsic expertise advantages. I feel this development will proceed and I feel the trouble even then might be stronger going ahead. As they have to be extra intertwined between expertise and the design, you would name it more durable? I feel it’s going to turn into extra delicate, and we have to work nearer with our clients to actually optimize issues collectively. Now you even have superior packaging coming in, so how a system can partition its expertise may fluctuate. When you have a chiplet, the way you architect it at a system stage from the get-go, you must take into consideration find out how to architect your system in the correct approach by leveraging completely different items of silicon expertise and completely different integration schemes.

Many due to Kevin, Maria, and TSMC’s Comms groups for his or her time.

Additionally due to Gavin Bonshor for transcription.

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